Characterization of MMIC DPAs: from wafer screening to system level

Date/Time: Wednesday, 24 January — 1:30pm – 2:30pm

Lecturer:  Anna Piacibello, Politecnico di Torino

Abstract

This talk will give an overview of the characterization flow for MMIC Doherty PAs, from the initial wafer screening to the performance assessment at system level. Doherty PAs require specific procedures to test the correct operation of its Main and Auxiliary branches, which are biased in different classes and therefore respond differently to signal excitations. This reflects in the way in which DC, small signal and large signal measurements are devised and carried out during the characterization flow. Finally, a short overview of the different metrics that can be used to estimate the PA linearity in different scenarios will be given.

Bio

Anna Piacibello received the bachelor’s and master’s degrees in electronic engineering and the Ph.D. degree in electric, electronic and communication engineering from the Politecnico di Torino, Turin, Italy, in 2013, 2015, and 2019, respectively.

In 2017, she was a Visiting Researcher with the Centre for High Frequency Engineering, Cardiff University, Cardiff, U.K. She is currently an Assistant Professor with the Department of Electronics and Telecommunications, Politecnico di Torino. Her research interests include the design and characterization of microwave and millimeter-wave electronic circuits, mainly focusing on broadband and highly efficient power amplifiers.

She has been an Affiliate Member of the IEEE MTT-S Technical Committee TC-12 on Microwave High-Power Techniques since 2022. She was a recipient of the 2018 Young Engineer Prize awarded by the European Microwave Association.

High Efficiency CMOS Power Amplifiers: Design Challenges and Outlook

Date/Time: Wednesday, 25 January — 3:40pm – 4:40pm

Lecturer:  Narek Rostomyan, Waveye, Inc.

Abstract

Power consumption of mm-wave communication and radar systems is a significant bottleneck for many applications due to size, cost, battery, and heatsinking constrains. Depending on the application, the RF front-end, and in particular the power amplifier, can be one of the main contributors to the overall power consumption. Additionally, both in communication and radar systems, the choice of the transmit waveform poses design constrains on the RF front-end architecture and achievable specifications.

It is well known that achieving high efficiency with on-chip silicon power amplifiers at mm-wave frequencies is quite challenging. This is due to the high peak-to-average power ratios of 5G NR waveforms, low quality factors of on-chip passive components, small breakdown voltages, and limited fmax of transistors. Furthermore, in order to attain high linearity without resource-hungry digital pre-distortion, a significant amount of back-off from Psat/P1dB is usually necessary, which penalizes the average efficiency even more. On the other hand, the choice of the transmit waveform has even more impact on the overall system architecture and ultimately the power consumption for modern mm-wave radars.

In this short course, we will review various challenges and techniques that affect the efficiency and linearity of mm-wave PAs in silicon technologies. We will also review various commonly used efficiency improvement techniques. Practical design challenges will be emphasized. Finally, we will conclude with a step-by-step case study of a single stage Ka-band Doherty amplifier design.

Bio

Narek Rostomyan earned his M.Sc. in electrical engineering from the Technical University of Munich, Germany, in 2014, and completed his Ph.D. in electrical engineering, specializing in RF/mm-wave transceivers and high-efficiency CMOS SOI power amplifiers, at the University of California, San Diego (UCSD), in 2018.

During his early career, from 2013 to 2014, he contributed to RF front-end design of mm-wave signal generators at Rohde & Schwarz in Munich, Germany. Later, from 2018 to 2020, he played a pivotal role in developing the first generation of 76-81 GHz automotive radar transmitter and receiver chipsets at Metawave in Carlsbad, USA. Subsequently, from 2020 to 2022, he served as a senior principal engineer at IQ-Analog in San Diego, focusing on mm-wave, broadband front-ends, and high-speed mixed-signal IPs for RF sampling, high-speed ADCs/DACs in FinFET CMOS.

Currently, Narek serves as the co-founder and Chief Innovation Officer (CIO) at Waveye, Inc. (Palo Alto, CA), leading efforts in next-generation mm-wave radar imaging and perception. His research interests encompass high power and efficiency CMOS integrated circuits and systems for wireless communication, radar, and sensing applications.